Electronics enthusiast with a passion for chips, semiconductor packaging, and debugging the trickiest signal integrity problems.
Deep-domain work spanning EM simulation, packaging co-design, and full-custom analog with hands-on cleanroom fabrication experience bridging design to silicon.
Extracting S-parameters, modeling interconnect parasitics, and characterizing PDN impedance for high-speed chiplet-based systems. Experienced with ANSYS HFSS for full-wave EM simulation of package and PCB structures including via transitions, trace routing, and decoupling strategies.
Building 2D/2.5D chiplet package models with interposer routing, micro-bump arrays, and RDL stackups. Analyzing warpage, CTE-driven strain, and thermo-mechanical reliability to inform SI/PI-aware co-design decisions across die-package-board boundaries.
Full design flow from schematic through simulation — folded-cascode amplifiers and multi-class RF power amplifiers in Cadence Virtuoso and Keysight ADS with DC, AC, and transient analysis across load and bias conditions.
Graduate training at ASU's semiconductor packaging and analog IC programs, built on a strong EE foundation from Mahindra University.
Simulation-driven projects spanning package-level SI/PI, transmission line characterization, RF power divider co-simulation, and full-custom analog design.
Package-level modeling study using ANSYS Mechanical to evaluate thermo-mechanical behavior and its impact on interconnect parasitics and signal/power integrity in chiplet architectures.
Full-wave electromagnetic simulation of a microstrip transmission line on aluminum nitride substrate in ANSYS HFSS, characterizing high-frequency interconnect behavior through S-parameter extraction across a wideband frequency sweep.
Microstrip Wilkinson power divider designed for the 5.65 to 5.925 GHz band on Rogers RO4003C substrate, validated through S-parameter analysis and Momentum EM co-simulation for return loss, power split balance, and port isolation.
Folded-cascode CMOS amplifier design in Cadence Virtuoso with transistor sizing, beta-multiplier biasing, and comprehensive DC/AC/transient simulation across load and bias conditions.
Comparative RF amplifier study across Class-A, Class-B, Class-C, and Doherty topologies evaluating efficiency and linearity through input power sweeps, output back-off analysis, and modulated signal characterization.
Python-based simulation of 0.5 um particle distribution in a 10x10x1 ft3 cleanroom slice, modeling zone-based recirculation, HEPA/ULPA filtration, and equipment blockages to determine ISO and Fed. Std. 209E cleanliness classifications.
Teaching, hardware development, and fabrication experience connecting design simulation to physical realization.
Supporting semiconductor fabrication cleanroom instruction and systems dynamics laboratory coursework.
Developed analog front-end circuits for solar energy sensing with emphasis on noise reduction and signal conditioning.
Developed IoT sensor modules with analog signal conditioning for industrial monitoring applications.
Tools and domain knowledge spanning EM simulation, package design, analog IC, and lab measurement organized by functional area.
Open to opportunities in Signal/Power Integrity engineering, advanced semiconductor packaging, and analog IC design.